The ADC ADC data acquisition component is a monolithic CMOS device with an 8-bit analog-to-digital con- verter 8-channel multiplexer and. ADC ADC – 8-bit Microprocessor Compatible A/D Converters With 8- Channel Multiplexer, Details, datasheet, quote on part number: ADC The ADC/ADC Data Acquisition Devices (DAD) implement on a single chip most the elements of the stan- dard data acquisition system. They contain.

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Once loaded the multiplexer sends the appropriate channel to the converter on the chip. All of the signals are explained below.

Analog to Digital Converter – ADC/ADC

That is because ADCs require clocking and can contain control logic including comparators and registers. Begin by downloading the files into your desired destination directory and then compile them in this order.

Address Lines Because the chip has an 8 channel multiplexer there are three address select lines: Clock The clock signal is required to cycle through the comparator stages to do the conversion.

C is the most significant bit and A is the least. Datsheet means it must remain stable for up to 72 clock cycles. The OE signal should conform to the same range as all the other control signals. The voltage level that, when received as an input, will output “” to the FPGA. The signal can be tie to the ALE signal when the clock frequency is below kHz.

As with all control signals it is required to have an input value of Vcc – 1. This means that in order to get it to work, there is a total of seven control signals that must be sent from the FPGA. Note that it can take fatasheet to 2. The source code provided was used to control an ADC where only 4 inputs were used, therefore, ADD C is tied to ground and so are the unused inputs. This means that an axc0809 conversion takes at least 64 clock cycles.


Up to 72 if the start signal is received in the middle of an 8 clock cycle period. It is a control signal from the FPGA, which tells the converter when to start a conversion. The source must remain stable while it is being sampled and should contain little noise.

All control signals should have a high voltage from Vcc – 1. Table 2 provides a summary of all of the input and output to the chip. It is the Second bit of the select lines. There are a daatasheet of limitations that follow: It is a pulse of at least dahasheet in width. Like the ALE pulse the minimum pulse width is ns. Modification to the source code are required to use more than just four channels.

National Semiconductor

Unfortunately you cannot just hook up analog inputs to an ADC and expect to get digital outputs from the chip without adding control datasyeet. Signal from the ADC. It can be tied to the Start line if the clock is operated under kHz. See table 1 for details. The other files are enabled register, a register, and a multiplexer. This is an address select line for the multiplexer. Source code The source code consists of a few of files.

Users can look for a rising edge transition. The maximum clock frequency is affected by the source impedance of the analog inputs. It goes low when a conversion is started and high at the end of a conversion.

You will also need to download multiplex. Bottom rail of Reference voltage. The minimum pulse width is ns.

If Vcc and ground are used as reference voltages, they should be isolated by decoupling with a 1 microF capacitor. At clock speeds greater than that the user must make certain that enough time has passed since the ALE signal was pulsed so that the correct address is loaded into the multiplexer before a conversion begins.


The following control signals are used to control the conversion. Top rail of Reference voltage. The signal goes low once a conversion is initiated by the start signal and remains low until a conversion is complete. The source resistance must be below 10kohms for operation below kHz and below 5kohms for operation around 1. It is recomended that the source resistance not exceed 5kohms for operation at 1. There are 8, 8 clock cycle periods required in order to complete an entire conversion. The ADC stores the data in a tri-state output latch until the next conversion is started, but the data is only output when enabled.

A, B, and C. For a quick reference refer to table 2. The start signal should conform to the same range as all other control signals.

On the rising edge of the pulse the internal registers are cleared and on the falling edge of the pulse the conversion is initiated. Start The purpose of the start signal is two fold.

Datxsheet is the MSB of the select lines.

The clock should conform to the same range as all other control signals. In this implementation the OE signal asc0809 pulsed high one clock cycle after the EOC signal goes high and remains high until the data is safely stored into the desired register in the FPGA.